The present invention relates generally to integrated circuit clock circuitry and more particularly to such clock circuitry including a receiver having an input impedance causing a wire carrying a clock wave to the receiver to present to a driver an impedance having a resistance-capacitance (RC) time constant that is a relatively small fraction of a cycle of the clock wave.
An integrated circuit (IC) chip frequently includes clock trees to distribute clock waves to physically separated destination (i.e., receiver) circuits. Typically, an off-chip, external clock source provides clock waves to a plurality of clock tree branches or segments resident on the IC chip. Each branch or segment of the clock tree carries clock waves to a respective one of the physically separated destination circuits.
Ideally, the clock waves delivered by any given branch arrive at the associated destination circuit in synchronism or in phase with the other clock waves arriving at their respective destination circuits. In this way, synchronism is maintained across the entire integrated circuit chip. In such an ideal case, the respective clock waves are said to exhibit zero clock skew at the various destination circuits. The term xe2x80x9cclock skewxe2x80x9d represents the relative time delay between corresponding clock waves as they exit their respective branches. For example, the clock skew between two branches of the clock tree is the time delay between the rising edges of corresponding clock waves exiting the two branches.
Although the ideal clock tree delivers clocks with zero skew, in reality, there are many factors that adversely affect, i.e., increase, clock skew in an IC chip, to prevent zero clock skew from being obtained throughout the chip. One factor is material processing variations inherent to the IC chip fabrication process; chip components can only be fabricated to predetermined tolerances so that different nominally identical components at different locations on the chip have different characteristics. Other factors include power supply and temperature variations across the chip. Since large IC chips are susceptible to both spatial and temporal variations in localized temperature and power supply voltage while operating, and since chip component characteristics and behavior are influenced by such variations, clock skew correspondingly varies both spatially and temporally across the chip. As the size of an IC chip increases, the variability of these factors and thus the variability of clock skew, worsens.
Large IC chips require clock lines of relatively long length to carry clock waves throughout the chip. In large chip applications, these relatively long clock lines and the delays they introduce, as well as the other factors affecting clock skew described previously, combine to exacerbate clock skew. In addition, the requirement to operate IC chips at high frequency (e.g., at 500 MHz or more), further requires tight control and clock skew minimization. Thus, an important challenge presented by increasing IC chip size and clock operating frequency is that of controlling clock skew to within acceptable tolerances.
FIG. 1 is a circuit diagram of a conventional clock tree distribution segment for distributing clock waves on an IC chip carrying the segment. The circuit of FIG. 1 is on an IC chip and includes spaced clock wave driver 4 and clock wave receiver 6 as well as wire or clock line 2 that is connected between the driver and receiver. Driver 4 usually responds to clock waves in the form of a sequence of clock pulses derived from a clock source (not shown) that is not on the IC chip. Driver 4 derives at output terminal 10 a sequence of amplified clock waves in the form of clock pulses. Terminal 10, at the junction of the drains of complementary field effect transistors 11 and 13 having gates driven in parallel by the clock pulses from clock input 12, is connected to a first end of single ended line 2 to supply the derived clock pulses to the first end of the clock line. The clock waves traverse clock line 2 and exit at a second end thereof to be injected into input terminal 14 of clock wave receiver 6.
Receiver 6 includes complementary FETs 17 and 19 having gates driven in parallel by the pulses at terminal 14 of line 2 and drains connected to a common terminal 16, where the output is derived. The FETs of driver 4 and receiver 6 are connected across power supply rails connected to DC power supply terminals +Vdd and ground so the sources of N-channel FETs 11 and 17 are grounded and the sources of P-channel FETs 13 and 19 are at +Vdd; in the typical prior art circuit, Vdd=3 Volts. The clock pulses propagating along line 2 are attenuated because of the substantial impedance of the line, are phased delayed because of the substantial resistance-capacitance (RC) time constant of the line, and are subject to noise on the line which is coupled to terminal 14. Receiver 6 responds to the degraded clock pulses at terminal 14 to amplify the pulses almost to the rail-to-rail voltages +Vdd and ground.
When a plurality of conventional clock tree distribution segments of the type illustrated in FIG. 1 distribute clocks across an IC chip, clock skew problems arise between the various clock distribution segments. One reason these conventional circuits contribute to clock skew is because they inherently impart large time delays to the clock waves. Since these circuits themselves introduce in part large time delays to the clock waves, even small changes or variations in this large delay, as between the various clock tree segments, contribute significantly to an increase in clock skew. These changes in the delay between the various clock segments arise as a result of small variations in operating characteristics and behavior of the individual components comprising the individual clock segments.
The following example serves to illustrate this point. Referring again to the conventional clock circuit of FIG. 1, assume that clock line 2 and input terminal 14 of receiver 6 together present an input impedance to output 10 of driver 4 on the order of several hundred ohms, due primarily to the high gate-source impedance FET receiver 6 presents to terminal 14 and the driver 4 output impedance, as well as the impedance of line 2. Typically, clock line 2 presents a capacitive load of approximately 2 pico farads (pF) to output terminal 10 of driver 4. With these exemplary assumptions, a typical RC time constant of approximately several hundred picoseconds is presented to the clock pulses at output terminal 10 of driver 4. In an integrated circuit chip operating at a frequency of, for example, 1 GHz, which translates to clock periods or cycles on the order of 1 nanosecond (ns), the several hundred ps time delay introduced by the conventional clock circuit of FIG. 1 represents a considerable portion of each half cycle pulse of each clock period. Thus, small changes in delay times between clock segments, due to the factors discussed previously, can cause clock skew of a considerable portion of one clock cycle. Clearly, for IC chips operating at high frequencies wherein clock synchronization across the chip is required, such clock skew is disadvantageous and the conventional clock circuit of FIG. 1 has substantial problems in controlling clock skew to within acceptable tolerances.
Although the foregoing approximation serves as a useful example to illustrate the adverse effect of the large interconnect delay of the circuit of FIG. 1 on clock skew, characterizing the RC delay on the interconnect mathematically is useful for comparative purposes. The following generalized equation, Equation (1), characterizes the total RC delay time (Delay) of clock line 2 between driver 4 and receiver 6                     Delay        =                                                            R                ⁢                                  xe2x80x83                                ⁢                int                ⁢                                  xe2x80x83                                ⁢                C                ⁢                                  xe2x80x83                                ⁢                int                            2                        ⁢                          (                                                Rdr                  +                                      R                    ⁢                                          xe2x80x83                                        ⁢                                          int                      /                      3                                                        +                  Rcvr                                                  Rdr                  +                  Rrcv                  +                                      R                    ⁢                                          xe2x80x83                                        ⁢                    int                                                              )                                +                      Rdr            ⁢                          xe2x80x83                        ⁢            C            ⁢                          xe2x80x83                        ⁢                          int              ⁡                              (                                  Rcvr                                      Rdr                    +                                          R                      ⁢                                              xe2x80x83                                            ⁢                      int                                        +                    Rcvr                                                  )                                                                        Eq        .                  xe2x80x83                ⁢                  (          1          )                    
In Equation (1), Rdr represents the resistive output impedance of driver 4, Rint represents the resistive impedance of clock line 2 seen by looking from the first end of the line into the line with a second end of the line connected to the line characteristic impedance, Rrcv represents the resistive input impedance of receiver 6 as seen by looking from terminal 4 into the gates of FET 17 and 19, and Cint represents the capacitive impedance of the clock line seen by looking from the first end of the line into the line with a second end of the line connected to the line characteristic impedance.
In the conventional clock circuit of FIG. 1, Rrcv is on the order of megaohms, whereby Rrcv greater than  greater than Rint and Rdr to enable Equation (1) to be approximated as follows:                     Delay        =                                            R              ⁢                              xe2x80x83                            ⁢              int              ⁢                              xe2x80x83                            ⁢              C              ⁢                              xe2x80x83                            ⁢              int                        2                    ⁢                      (                          1              +                                                2                  ⁢                  Rdr                                                  R                  ⁢                                      xe2x80x83                                    ⁢                  int                                                      )                                              Equation        ⁢                  xe2x80x83                ⁢                  (          2          )                    
Having established RC delay for the conventional circuit, as represented in Equation (2), it then follows that the skew due to variations in Rint and Cint due to the variable factors discussed previously, such as material processing, power supply voltage and temperature variations, can be expressed as:                     Skew        =                                                            δ                ⁡                                  (                                      R                    ⁢                                          xe2x80x83                                        ⁢                    int                                    )                                            ⁢              C              ⁢                              xe2x80x83                            ⁢              int                        2                    ⁢                      (                                          2                ⁢                                  xe2x80x83                                ⁢                Rdr                                            R                ⁢                                  xe2x80x83                                ⁢                int                                      )                                              Equation        ⁢                  xe2x80x83                ⁢                  (          3          )                    
Equation 3 assumes that the product Rint*Cint is a constant, which is generally the case.
Since the denominator term, Rint, in Equation 3 is a relatively small quantity, e.g., a few ohms, compared to the product of the terms in the numerator, skew in the conventional circuit is relatively large. The conventional clock circuit of FIG. 1 is generally characterized as a voltage mode interconnection or clock circuit because of the very high gate source input impedance of FET receiver 6, the receiver being primarily responsive to voltage swings at its input. Thus, Equations (2) and (3) respectively characterize the relatively large RC time delay and corresponding clock skew for the conventional voltage mode interconnection or clock circuit of FIG. 1.
One solution proposed in the prior art for controlling skew is to provide driver and receiver pairs that operate at higher current and power levels. However, this approach causes large current switching transients to substantially increase power dissipation and noise on DC power supply lines. Consequently, operating at higher current and power levels has substantial disadvantages. In summary, there is a need to reduce and control clock skew in clock distribution networks on IC chips without substantially increasing power dissipation or introducing undue switching noise on the IC chip.
Clock circuitry on the IC chip is subject to noise and problems associated therewith. Particularly, noise is introduced onto the single ended clock line coupled between the single ended driver and single ended receiver pair associated with that clock line. The amount of noise coupled to clock lines increases with increases in IC chip size, since the clock lines are necessarily longer in the larger chips.
In the conventional, prior art clock circuit of FIG. 1, noise introduced onto clock line 2 corrupts the integrity of the clock pulses propagating between driver 4 and receiver 6. Since receiver 6 is not inherently immune to noise and does not provide noise correction or elimination, clock line noise arriving at input terminal 14 of receiver 6 is simply coupled to the output of receiver 6, and/or the noise translates to clock jitter at the receiver output terminal 16. Clock pulses with substantial noise components superimposed thereon arrive at destination circuits a responsive to the output of receiver 6. Under such conditions, the destination circuits of the IC chip usually do not have optimum performance. Thus, there is a need to eliminate or substantially reduce the effects of noise introduced onto the clock lines between the driver and receiver of a clock circuit, to provide a substantially noise free clock wave to a destination circuit on the IC chip.
In summary, there is a need to provide IC chip clock circuitry that both reduces clock skew and/or minimizes the deleterious effects caused by noise coupled onto clock lines in the chip. There is a further need to achieve these goals in the environment of large IC chips operating at high frequencies.
It is accordingly an object of the present invention to provide new and improved integrated circuit clock circuitry having reduced clock skew.
A further object of the present invention is to provide a new and improved clock circuit for reducing clock skew on an IC chip operating at high clock wave frequencies.
An additional object of the present invention is to provide new and improved clock circuitry arranged to minimize the deleterious effects caused by noise coupled onto clock lines in an IC chip.
In one aspect of the present invention, a clock circuit on an IC chip includes a driver having an output for supplying an output clock wave to a receiver via a clock line, wherein the receiver has a resistive input impedance causing the clock line to present to the driver output an impedance having a resistance-capacitance (RC) time constant that is a relatively small fraction of a period of the clock wave.
In another aspect of the present invention, the receiver includes a shunt impedance coupled between an output terminal of the clock line and a DC power supply line, wherein the shunt impedance has a resistance approximately equal to an output resistance of the driver. The receiver also includes a current source arranged to supply current to the shunt impedance and through the clock line to an output impedance of the driver. This arrangement causes the resistance seen by the driver looking into the line to be relatively low, to enable the RC time constant seen by the driver to be a relatively small fraction of a period of the clock wave.
In a further aspect of the present invention, the driver includes a first transistor having a first current path and an impedance connected between the driver output terminal and a first power supply line. The first transistor includes a first control electrode responsive to the clock wave of the clock wave source for controlling the impedance of said first current path. The receiver shunt impedance includes a first device, configured as a diode, and connected between the line output terminal and the first DC power supply line. The first device is respectively conducting and non-conducting responsive to a clock wave voltage at the input of the receiver having relatively high and low levels. The receiver includes a second device, configured as a diode, and connected between an output terminal of the receiver and the second power supply line. The second device is respectively conducting and non-conducting responsive to a voltage at the receiver output terminal having relatively low and high levels relative to the first power supply line. The receiver further includes a second transistor having a second current path and an impedance connected in parallel with the second device. The second transistor includes a second control electrode for driving the impedance of the second current path relatively high and low when the second device is respectively conducting and non-conducting. The receiver includes a third device, configured as a current source, and connected between the input and the output of the receiver. The third device includes a control terminal for controlling the current the third device supplies to the shunt impedance.